The active matrix display employs a thin film circuit at each pixel that allows each pixel in the display to be directly addressed. In a typical active matrix liquid crystal display (AMLCD), each pixel circuit includes a data thin film transistor (TFT) T1 connected between a data line Vdata and a liquid crystal display cell LCD and storage capacitor C pair, as shown in FIG. 1. The thin film transistor has a control gate G1 connected to an enable voltage Venable. During operation, a data voltage Vdata is placed on drain D of transistor T1 and, when gate G1 is activated, data voltage Vdata is transferred to storage capacitor C and liquid crystal cell LCD though TFT T1. The power dissipated during the charging of capacitor C and liquid crystal display cell LCD is usually negligible. The power problem in the AMLCD is typically in a backlight circuit that supplies the light, which the LCD modulates. In the case of active matrix emissive displays, particularly the active matrix organic light emitting displays (AMOLED), significant amount of power is consumed to produce light emissions from the pixels, and additional power is required to operate driving circuits in the active matrix, which control the light emissions.
With reference to FIG. 2, a typical driving circuit of an organic light-emitting diode (OLED) active matrix emissive display includes an OLED D1 and a power TFT T2 serially coupled with each other between a voltage supply VDD and ground. TFT T2 has a source S connected to OLED D1, a drain D connected to voltage supply VDD, and a gate G2 connected to TFT T1. Capacitor C is coupled between the source S and gate G2 of TFT T2. OLED D1 has parasitic resistor RD and parasitic capacitor CD. TFT T2 supplies current ID to OLED D1. The level of emissions from OLED D1, or, in a more scientific term, the luminance of OLED D1, is proportional to the current ID. Since the voltage across TFT T2 and OLED D1 is equal to VDD, the power P dissipated by TFT T2 and OLED D1 is equal to VDD times the current ID While the voltage supply VDD is divided between TFT T2 and OLED D1, the same current ID flows through both. Therefore, the power P is divided between TFT T2 and OLED D1 in proportion to the voltage VDD being divided between them.
Before any current is supplied to OLED D1 by TFT T2, the source S of TFT T2 is at ground state causing the voltage VDD to fall almost entirely across TFT T2. As current ID increases in OLED D1, the voltage VD across TFT T2 decreases, while the sum of the voltage across OLED D1 and voltage VD equals VDD. A problem arises because OLED D1 is a load on TFT T2, which load is changing during operation, as every level of luminance from OLED D1 requires a specific current ID, and thus, represents a different load to TFT T2. In order to faithfully convert data voltage Vdata to a specified current ID and a specified luminance of OLED D1 corresponding to Vdata, changes in the load of TFT T2 due to changes in the luminance of OLED D1 should not cause changes in current ID output from TFT T2. That is, TFT T2 should act as a current source and not change current output as the load changes. In order for TFT T2 to act as a current source, voltage VD across TFT T2 must bias TFT T2 in the saturation mode. As shown in FIG. 3, the saturation mode corresponds to the flat part of each ID versus VD curve, while the steep slope leading up to the flat part corresponds to the unsaturated mode.
In the saturation mode, ID depends almost entirely on VG, which is the voltage on gate G of TFT T2, as expressed in Eq. 1:
                              I          D                =                                            μ              ·                              ε                0                            ·                              ε                r                            ·              w                                      2              ·              d              ·              1                                ⁢                                    (                                                V                  G                                -                                  V                  th                                            )                        2                                              (        1        )            where μ,ε0, εr, W, l, d, and Vth are parameters associated with TFT T2. with μ being the effective electron mobility, ε0 being the permittivity of free space, εr being the dielectric constant of the gate dielectric, w being the TFT channel width, l being the TFT channel length, d being the gate dielectric thickness, and Vth being the threshold voltage.
For a TFT to be in the saturation mode, VD must be greater than VG−Vth. Thus, for a specified current ID 
                                          V            D                    >                                    V              G                        -                          V              th                                      =                                            I              D                        ⁢                                                  ⁢                                          2                ·                d                ·                1                                            μ                ·                                  (                                                            ε                      0                                        ·                                          ε                      r                                        ·                    w                                    )                                                                                        (        2        )            
Typically, 1 μA of current is sufficient to give bright emissions from an OLED pixel. Following are examples of TFT parameters:                Vth≈1 V        μ≈0.75 cm2/V·sec        εr≈4        w≈25 μm        1≈5 μm        d≈0.18 μmfrom which it is estimated that:VD<VG−Vth≈5.206V, for ID=1 μA.        
This means that the minimum VD required to put TFT T2 in saturation is about 5.2V for a drain current of 1 μA, or that at ID=1 μA, the power dissipated by TFT T2 is about 5.2 microwatts. This estimate is for an ideal situation. In practice, a larger voltage across the OLED is needed to pass 1 μA of current through the OLED as the OLED ages. For example, when an OLED is new, only about 4 V across the OLED is required to pass 1 μA of current, but as it ages this voltage may increase to as high as 6 volts. This means that 2 extra volts should typically be added to VDD to ensure that TFT T2 stays in saturation over the lifetime of the display. In addition, if higher OLED luminance is desired, higher VD will be required to ensure saturation. Furthermore, even higher VD may be required to keep TFT T2 in saturation due to threshold voltage drift, which often happens with amorphous silicon TFTs. Thus, the total required voltage VD is about 5.2 V for an ideal case when 1 μA of drain current is generated in the saturation mode, plus about 2 volts for threshold voltage drift and about an additional 2 volts for OLED aging and maximum OLED brightness. This means that VDD needs to be as high as about 13.2 volts. This also means that when the display is new, for 1 microampere of current through the OLED D1, there will be about 4 volts across the OLED and about 4 microwattts of power dissipation by the OLED, while about 9.2 volts of voltage is across TFT T2 and power dissipation by the TFT is about 9.2 microwatts, which is more than twice the power dissipation of the OLED itself.
Thus, there is a need for a display that provides good control of pixel luminance without excessive power dissipation by the power TFTs.